Senior FPGA Engineer

Contemporary satellites are commonly constructed in a modular fashion, divided into distinct units, each dedicated to a specific function. In adopting a vertical integration approach, Aerospacelab, as a satellite manufacturer, designs a wide variety of these units. Leveraging the FPGA’s flexibility and reprogrammability makes it an excellent choice as the foundational technology for our units. 

As our portfolio of FPGA-based units grows, we are looking for a Senior FPGA Engineer to take technical ownership of that gateware: someone who can shape architecture from system requirements, raise the bar on design and verification quality, and grow the engineers around them. 

You will join one of our agile development teams built around a specific unit: on-board computers, software defined radios, image sensors, optical transceivers, network switches or telecommunication payload and act as the FPGA technical reference for that team. Beyond writing RTL yourself, you will own the FPGA architecture, make and defend the key design trade-offs, mentor junior and mid-level engineers, and lead small groups of FPGA engineers on the more complex units. 

These units bring challenging signal and image processing algorithms, innovative optical solutions and high-throughput routing. Communication and cooperation across competences are central: you'll work closely with PCB designers (EE) and embedded software engineers, and, depending on the project: RF, optical or network engineers. You'll often be the person translating between system intent and gateware reality. 

At Aerospacelab, our motto is work hard, play hard. We strive to innovate in a fun and inclusive environment, and we work in short cycles: no waiting years before code goes live and earns valuable feedback. Expect a role where your decisions shape state-of-the-art gateware that rapidly makes its proof in orbit. 

• Answer challenging requirements with innovative, well-justified architectural solutions 
• Cope with the constraints of the space environment 
• Create critical, high-quality gateware and the verification that proves it 
• Set and uphold design, documentation and verification standards across the team 
• Mentor FPGA engineers and lead small FPGA teams on complex units 

• RTL: VHDL 
• Simulation: Questasim, Makefile, Python, TCL 
• Tests on target: Makefile, Embedded-C, Embedded-Linux, FreeRTOS, Python 
• CI/CD: Gitlab, Docker